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The Verillog® Hardware Description Language

The Verillog® Hardware Description Language

Donald E. Thomas, Philip R. Moorby (auth.)
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xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("

年:
2002
出版:
5
出版社:
Springer US
语言:
english
页:
382
ISBN 10:
1402070896
ISBN 13:
9781402070891
文件:
PDF, 7.95 MB
IPFS:
CID , CID Blake2b
english, 2002
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